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Written by Hamid Noori   
Monday, 10 February 2014 05:24

Journal

1-      H. Noori, F. Mehdipour, K. Inoue, and K. Murakami, “Improving Performance and Energy Efficiency of Embedded Processors via Post-Fabrication Instruction Set Customization”, The Journal of Supercomputing, Vol. 60, Issue 2, Page 196-222, 2012.

2-      M. Goudarzi, T. Ishihara, and H. Noori, “Software-Level Instruction-Cache Leakage Reduction Using Value-Dependence of SRAM Leakage in Nanometer Technologies”, Transaction on High-Performance Embedded Architectures and Compilers (HiPEAC), Vol. 3, No. 4, pp. 275-299, 2011.

3-      F. Mehdipour, H. Noori, K. Inoue, and K. Murakami, “Rapid Design Space Exploration of a Reconfigurable Instruction-Set Processor”, IEICE Transaction on Fundamentals of Electronics, Communications and Computer Sciences, Special Section on VLSI Design and CAD Algorithms, Vol. E92-A, No. 12, pp. 3182-3192, December 2009. 

4-      H. Noori, F. Mehdipour, K. Murakami, K. Inoue, and M. Saheb Zamani, “An Architecture Framework for an Adaptive Extensible Processor”, The Journal of Supercomputing, Springer Netherlands, Vol. 45, No. 3, pp. 313-340, September 2008.

5-      F. Mehdipour, H. Noori, H. Honda, K. Inoue, and K. Murakami, “A Gravity-Directed Temporal Partitioning Approach”, IEICE Electronics Express (ELEX), Vol. 5, No. 10, pp. 366-373, May 2008.

6-      H. Noori, M. Goudarzi, K. Inoue, K. Murakami, “Temperature-Aware Configurable Cache to Reduce Energy in Embedded Systems”, IEICE Transaction on Electronics, Special Issue on Advanced Technologies on Digital LSIs and Memories, Vol. E91-C, No. 4, pp. 418-431, Apr. 2008.

7-      H. Noori, F. Mehdipour, K. Inoue, and K. Murakami, “A Reconfigurable Functional Unit with Conditional Execution for Multi-Exit Custom Instructions”, IEICE Transaction on Electronics, Special Issue on Advanced Technologies on Digital LSIs and Memories, Vol. E91-C, No. 4, pp.497-508, Apr. 2008.

8-      F. Mehdipour, H. Noori, M. Saheb Zamani, K. Inoue, and K. Murakami, “Improving Performance and Energy Saving in a Reconfigurable Processor via Accelerating Control Data Flow Graphs”, IEICE Transactions on Information and Systems, Special Issue on Reconfigurable Systems, Vol. E90-D, No. 12, pp. 82-92, December 2007.

 

 

Conference & Workshop

 

1-      M. Baharani, M. Aliasgari, M.R. Najafi, H. Noori and M.R. Jamali, “A Neuro-Fuzzy Edge Based Spectrum Sensing Processor for Cognitive Radios”, IEEE East-West Design & Test Symposium (EWDTS 2012), Kharkov, Ukraine, 2012.

2-     نیلوفر قاسمی، سمانه طالبی، علی جهانیان و حمید نوری "ارائه‌ی معماری و دستورالعمل‌های سفارشی جدید برای سفارشی‌سازی معماری پردازنده‌ی جاوا با هدف بهبود کارایی این نوع پردازنده"، بیستمین کنفرانس مهندسی برق ایران، 2012، تهران، ایران

3-      S. Abbaspour, M. Kamal, H. Noori, S. Safari, “Securing Embedded Processors against Power Analysis based Side Channel Attacks using Reconfigurable Architecture”, 9th IEEE/IFIP International Conference on Embedded and Ubiquitous Computing (EUC 2011), 2011, Melbourne, Australia.

4-      M. Taherian, A. Baniasadi and H. Noori, “Instruction and Data Cache Peak Temperature Reduction Using Cache Access Balancing in Embedded Processors”, 9th ACS/IEEE International Conference on Computer Systems and Applications (AICCSA), 2011, Sharm El-Sheikh, Egypt.

5-      A. Ghofrani, F. Javaheri, H. Noori and Z. Navabi, "Transaction Level Formal Verification using Timed Automata",  IEEE Eleventh workshop on RTL and high level testing (WRTLT'10) in conjunction with the 19th Asian Test Symposium (ATS'10), 2010, Shanghai, China.

6-      A. Yazdanbakhsh, M. Kamal, M. Salehi, H. Noori and S. M. Fakhraie, “Energy-Aware Design Space Exploration of RegisterFile for Extensible Processors”,
International Conference on Embedded Computer Systems: Architectures, MOdeling and Simulation
(SAMOS X), 2010, Samos, Greece.

7-      M. Kamal, N. Kazemian, A. Kamran, A. Hoseini, M.DehYadegari and H. Noori, “Dual-Purpose Custom Instruction Identification Algorithm based on Particle Swarm Optimization”, 21st IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP), 2010, Rennes, France.

8-      T. Hanada, Sh. Ueno, H. Noori, F. Mehdipour, K. Inoue and K. Murakami, “High-Performance, Low-Energy Embedded Computing Platform with ALU-Array based Accelerator”, Designing for Embedded Parallel Computing Platforms: Architecture, Design Tools and Applications Workshop in conjunction with DATE 2010, 2010, Germany.

9-      M. Lotfinejad, M. Mosleh and H. Noori, “A Novel Generic Three-Moduli set and its Optimum Arithmetic Residue to Binary converter”, The 2nd International Conference on Computer and Automation Engineering (ICCAE), 2010, Singapore.

10-  K. Inoue, H. Noori, F. Mehdipour, T. Hanada, and K. Murakami, "ALU-Array based Reconfigurable Accelerator for Energy Efficient Executions", International SoC Design Conference (ISOCC), 2009, Busan, Korea (invited paper).

11-  M. Lotfinejad, M. Mosleh and H. Noori, “A Novel High Speed Residue to Binary Converter Design Based on the Three Moduli Set {2n, 2n+1+1, 2n+1-1}”, 7th IEEE East-West Design & Test Symposium (EWDTS), 2009, Moscow, Russia.

12-  H. Ahmadinejad, S. Safari, and H. Noori, “Custom Instruction Selection for Extensible Processors with Power Reduction Target”, 7th IEEE East-West Design & Test Symposium (EWDTS), 2009, Moscow, Russia.

13-  F. Mehdipour, H. Noori, B. Javadi, H. Honda, K. Inoue, and K. Murakami, “A Combined Analytical and Simulation-Based Model for Performance Evaluation of a Reconfigurable Instruction Set Processor”, 14th Asia and South Pacific Design Automation Conference (ASP-DAC), 2009, Yokohama, Japan.

14-  F. Mehdipour, H. Noori, B. Javadi, H. Honda, K. Inoue, and K. Murakami, “Performance Evaluation of a Reconfigurable Instruction Set Processor”, International SoC Design Conference (ISOCC), 2008, Seoul, Korea (invited paper).

15-  H. Noori, F. Mehdipour, K. Inoue, and K. Murakami, “Enhancing Energy Efficiency of Processor-based Embedded Systems through Post-Fabrication ISA Extension”, International Symposium on Low Power Electronics and Design (ISLPED’08), 2008, Bangalore, India.

16-  H. Noori, M. Goudarzi, K. Inoue, K. Murakami, “Improving Energy Efficiency of Configurable Caches via Temperature-Aware Configuration Selection”, IEEE Computer Society Annual Symposium on VLSI, (ISVLSI 2008), 2008, Montpellier, France.

17-  F. Mehdipour, H. Noori, M. SahebZamani, K. Inoue, and K. Murakami, “Design Space Exploration for a Coarse Grain Accelerator”, 13th Asia and South Pacific Design Automation Conference (ASP-DAC), 2008, Seoul, Korea.

18-  M. Goudarzi, T. Ishihara, and H. Noori, “Variation-Aware Software Techniques for Cache Leakage Reduction Using Value-Dependence of SRAM Leakage Due to Within-Die Process Variation”, International Conference on High Performance Embedded Architectures & Compilers (HiPEAC), LNCS 4917, pp. 224-239, 2008, Goteborg, Sweden.

19-  H. Noori, F. Mehdipour, M. Goudazri, S. Yamaguchi, K. Inoue, and K. Murakami, “Energy Consumption Evaluation of an Adaptive Extensible Processor”, Second Annual Reconfigurable and Adaptive Architecture Workshop (RAAW) held in conjunction with the 40th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO), 2007, Chicago, Illinois, USA.

20-  F. Mehdipour, H. Noori, K. Inoue, and K. Murakami, “High-Performance, Low-Energy Reconfigurable Processor for Embedded Systems”, International SoC Design Conference (ISOCC), 2007, Seoul, Korea (invited paper).

21-   H. Noori, M. Goudarzi, K. Inoue, and K. Murakami, “The Effect of Nanometer-Scale Technologies on the Cache Size Selection for Low Energy Embedded Systems”, International Conference on Embedded Systems & Applications (ESA’07), 2007, Las Vegas, USA.

22-   H. Noori, K. Murakami, and K. Inoue, “An Architecture Framework for an Adaptive Extensible Processor”, 10th Annual ACM/SIGDA Ph.D. Forum at Design Automation Conference (DAC), 2007, San Diego, USA.

23-   H. Noori, F. Mehdipour, M. SahebZamani, K. Inoue, and K. Murakami, “Handling Control Data Flow Graphs for a Tightly Coupled Reconfigurable Accelerator”, International Conference on Embedded Software and Systems (ICESS-07), 2007, Daegu, Korea.

24-   H. Noori, F. Mehdipour, K. Murakami, K. Inoue and M. Goudarzi, “Generating and Executing Multi-Exit Custom Instructions for an Adaptive Extensible Processor”, Design Automation and Test in Europe (DATE’07), 2007, Nice, France.

25-   H. Noori, M. Goudarzi, K. Inoue, and K. Murakami, “The Effect of Temperature on Cache Size Tuning for Low Energy Embedded Systems”, The 17th edition of ACM Great Lakes Symposium on VLSI (GLSVLSI ), 2007, Stresa, Italy.

26-           F. Mehdipour, H. Noori, M. Saheb Zamani, K. Murakami, M. Sedighi and K. Inoue, “An Integrated Temporal Partitioning and Mapping Framework for Handling Custom Instructions on a Reconfigurable Functional Unit”, The 11th Asia-Pacific Computer Systems Architecture Conference (ACSAC 2006), LNCS 4186, pp. 219-230, 2006, Shanghai, China.

27- H. Noori, Farhad Mehdipour, K. Murakami, K. Inoue and M. Saheb Zamani, “A Reconfigurable Functional Unit for an Adaptive Dynamic Extensible Processor”, 16th IEEE International Conference on Field Programmable Logic and Applications (FPL 2006), pp. 781-784, 2006, Madrid, Spain.

28- F. Mehdipour, H. Noori, M. Saheb Zamani, K. Murakami, K. Inoue and M. Sedighi, “Custom Instruction Generation Using Temporal Partitioning Techniques for a Reconfigurable Functional Unit”, The IFIP International Conference on Embedded and Ubiquitous Computing (EUC-06), LNCS 4096, pp. 722-731, 2006, Seoul, Korea.

29-  F. Mehdipour, M. Saheb Zamani, M. Sedighi, Kazuaki Murakami and H. Noori, “GifT:  A Gravity-Directed and Life-Time Based Algorithm for Temporal Partitioning of Data Flow Graphs”, Engineering of Reconfigurable Systems and Algorithms 2006, (ERSA'06), Las Vegas, USA.

30-   H. Noori and Kazuaki Murakami, “Preliminary Performance Evaluation of an Adaptive Dynamic Extensible Processor for Embedded Applications”, 21st ACM Symposium on Applied Computing-Track on Embedded Systems: Applications, Solutions, and Techniques (SAC-EMBS), 2006, Dijon, France.

31- H. Noori, K. Murakami and K. Inoue, “General Overview of an Adaptive Dynamic Extensible Processor”, Workshop on Introspective Architecture (WISA) held in conjunction with the 12th international symposium on High-Performance Computer Architecture (HPCA-12), 2006, Texas, Austin, USA.

32-   H. Noori, N. Yoshimatsu, Y. Fujii, K. Eshima, M. Yoshida, T. Soga, T. Hayashida, K. Murakami,An Online Profiling-Based Dynamically Adaptable Processor”, Computer Society of Iran Computer Conference 2006 (CSICC 2006), Tehran, Iran.

33-  H. Noori, K. Eshima, Y. Fujii, M. Yoshida, T. Soga, N. Yoshimatsu, T. Hayashida and K. Murakami, “SysteMorph: An SoC Framework for Adaptive Dynamic Optimization Systems”, International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA’05), 2005, Las Vegas, USA.

34-  H. Safizadeh, H. Noori, M.Sedighi, A. Jahanian and N. Zolfaghari, “Efficient Host-Independent Coprocessor Architecture for Speech Coding Algorithms”, 8th EUROMICRO Conference on Digital System Design, 2005 (DSD’2005) , Porto, Portugal.

35-  M. Sedighi, H. Noori, H. Safizadeh, A. Jahanian and N. Zolfaghari, "Empowering RISC Processors for Speech Coding Algorithms Using a Portable Coprocessor Architecture", Electronic Design Process (EDP) Workshop 2004, Monterey, CA, USA.

36-  Sh. H. ShahHosseini, A. Samadi and H. Noori, “FPGA Implementaion of a 22 Gbps AES Encrypter”, 2nd Iranian Society of Cryptology Conference on Cryptology, Communications & Computer Security (ISCC 2003), 2003, Tehran, Iran, (in Persian).

37-  Sh. H. ShahHosseini, A. Samadi and H. Noori, “Using Memories for Implementing AES Algorithm”, 11th Iranian Conference on Electrical Engineering (ICEE 2003), 2003, Shiraz, Iran, (in Persian).

38-  H. Noori, H. Pedram, A. Akbari and Sh. Sheidaei,An FPGA Implementation of a DSP Core for FR, HR and EFR GSM Vocoders”, 9th International Symposium on Integrated Circuits, Devices & Systems (ISIC 2001), pages 327-330, 2001, Singapore.

39-  Sh. Sheidaei, H. Noori, A. Akbari and H. Pedram,Motivation from a Full-Rate Specific Design to a DSP Core Approach for GSM Vocoders”, 11th International Conference on Field Programmable Logic and Applications (FPL 2001), pages 388-397, 2001, Belfast, Northern Irland, UK.

40-  A. Arfaee, A. Akbari, K. Naderi and H. Noori,Design and FPGA implementation of a Fast MAC for GSM Vocoders”, 9th Iranian Conference on Electrical Engineering (ICEE 2001), pages 2-1 to 2-8 (132-com), 2001, Tehran, Iran (Persian).

41-  H. Noori, H. Pedram, A. Akbari and Sh. Sheidaei,FPGA implementation of a DSP Core for Full Rate and Half Rate GSM Vocoders”, 12th International Conference on Microelectronics (ICM 2000), pages 273-276, 2000, Tehran, Iran.

Last Updated on Thursday, 28 January 2016 15:00